The proper performance of a non-volatile memory device requires that the device retain data programmed into a memory cell within the device. The retention of the data requires that an electrical charge placed on an element of the non-volatile memory cell, such as a floating gate electrode, remain until such time as the cell is erased. Leakage of electrical charge from the floating gate electrode through the underlying dielectric layers and into the semiconductor substrate is a common failure mode of nonvolatile memory devices.
Over the lifetime of a non-volatile memory device, the memory cell is programmed and erased hundreds or even thousands of times. With prolonged use, the tunnel dielectric layer separating the floating gate electrode from the channel region of the floating gate transistor undergoes massive stress as electrical charge is repeatedly transferred through the dielectric layer. Charge transfer induced stress in the tunnel dielectric layer can result in the formation of defects within the dielectric layer and in severe cases, complete cracking of the dielectric material. When this happens, electrical charge leaks away from the floating gate electrode, thus changing the electrical potential of the electrode. This condition is known as data retention failure.
In processing methods of the prior art, a memory cell is fabricated by forming a tunnel region in a semiconductor substrate below the floating gate electrode. Typically, the tunnel region is formed by implanting N-type dopant atoms through a sacrificial oxide layer overlying the semiconductor substrate and into the substrate. A window is then opened in the sacrificial oxide layer exposing the semiconductor substrate, and an oxidation process is carried out to form a thin tunnel dielectric layer overlying the substrate surface. Once the tunnel dielectric layer is formed, a floating gate electrode is defined to overlie the tunnel dielectric layer. During subsequent processing steps, regions of high stress in the semiconductor substrate can result in a non-uniform redistribution of the implanted dopant atoms. One region of severe stress is located at the edge of field oxide regions used to isolate neighboring non-volatile memory cells from one another.
The migration of dopant atoms near the high stress locations leads to localized thinning of the field oxide regions and the tunnel dielectric layer near the interface of the two layers. For example, during fabrication, the field oxide regions encroach into active device regions creating a "bird's beak" structure. The implanted dopant atoms migrate to the bird's beak region and enhance the localized etching of the field oxide and the tunnel dielectric layer during subsequent etching steps carried out to fabricate the device. The localized thinning of the tunnel dielectric layer leads to erratic erasing behavior and reduces the durability of the tunnel dielectric layer resulting in early breakdown. Additionally, the implanted dopant atoms roughen the surface of the semiconductor substrate creating additional stress in the vicinity of the tunnel dielectric layer.
The aforementioned processing methods of the prior art compound substrate stress in the vicinity of the tunnel dielectric layer leading to early voltage breakdown of the dielectric layer. The tunnel dielectric layer prematurely wears out during programming and erasing operations leading to random single bit data retention failure. Accordingly, process improvements are necessary to enhance the reliability and long term performance of non-volatile memory devices.